Issue No. 2, August

Abstract

In the recent years a notable progress in the miniaturisation of electronic devices has been achieved in which the main component that has shown great interest is electronic memory. However, miniaturisation is reaching its limit. Alternative materials, manufacturing equipment and architectures for the storage devices are considered. In this work, an investigation on the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices is presented. Silicon nanostructures have attracted attention due to their small size, interesting properties and their potential integration into electronic devices. The two-terminal memory devices presented in this work, have a simple structure of silicon nanowires sandwiched between dielectric layers (silicon nitride) on glass substrate with thermally evaporated aluminium bottom and top contacts. The silicon nanostructures and the dielectric layer were deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) technique. The electrical behaviour of the memory cell was examined by Current-Voltage (I-V), data retention time (Current-time) and write-read-erase-read measurements. Metal-Insulator-Semiconductor (MIS) structures were also prepared for further analysis. The same silicon nanowires were embedded into the MIS capacitors and Capacitance-Voltage (C-V) analysis was conducted. Strong I-V and C-V hysteresis as well as an electrical bistability were detected. The memory effect is observed by this electrical bistability of the device that was able to switch between high and low conductivity states.

Abstract

Which parameter dominantly decides the value of time required to reset ReRAM (t_reset) among possible parameters, the value of a low resistance (R_L), voltage to induce reset (V_reset), and temperature to induce reset (T_reset)? Although to answer this question is important to achieve faster resistive switching, detailed correlations between the parameters are still unclear. In this paper, we extracted t_reset, V_reset, R_L and T_reset at the same time by combining two electrical measurements. As a result, we found a clear correlation between V_reset, R_L, and T_reset, meaning that each parameter can not be controlled independently. T_reset increases not only with increasing V_reset but also with increasing R_L, which suggests the necessity of introducing ununiformly-shaped filamens and resistive switching takes place at the narrowing part of the filament.

Abstract

It is important to specify the Cu diffusion path in the oxide layer of a Cu/oxide/Pt-structured conducting-bridge random access memory (CB-RAM), in terms of both the elucidation of resistive switching mechanism and optimization of memory performance. A first-principle calculation is effective in specifying the Cu diffusion path with atomic resolution. However, reported results of first-principle calculations are based on too simplified model to depict the actual system of CB-RAM. In this paper, a periodic slab model for the first-principle calculation of Cu diffusion process in HfO₂-CB-RAM was proposed based on experimental results. Both the most probable Cu diffusion surface and Cu diffusion path were suggested by the first-principles calculations based on the model. It was also suggested that the Cu diffusion path was modified by introducing oxygen vacancy into the Cu diffusion surface.

Abstract

The resistive switching behavior of a low resistive p-type α-Fe₂O₃ thin film sandwiched between Fe bottom electrode and top electrodes of various materials (Fe, Ni and TiN) was studied by current-voltage measurements. When TiN was used for top electrode of memory cell, the reversible resistive switching behavior was observed for over 100 cycles. From impedance measurement, it was suggested that the resistive switching behavior in the TiN/p-type α-Fe₂O₃/Fe device is attributed to the change of the contact resistance in the interface between TiN and α-Fe₂O₃ layers.

Abstract

This work illustrates a novel device for storing electronic charge and works as a nonvolatile memory device. It is fabricated using an industrial technique and consists of silicon nanostructures and diamond like carbon (DLC) as a memory element and an ultra-thin barrier layer respectively. Both the silicon nanostructures and the DLC have been deposited by plasma enhanced chemical vapour deposition (PECVD) technique. The nanostructures are sandwiched between two DLC layers. To understand the ability of silicon nanostructures to store electronic charge currentvoltage (I-V) and current-time (I-t) measurements were carried out. The memory effect is noted as the difference between the two electrical conductivity states (low ‘‘0’’ and high ‘‘1’’).

Abstract

In this paper, a non-volatile memory device based on a blend of metal oxides (Known as NiO) and polymer has been investigated. These devices have shown to display memory effects; a marked difference in electrical conductivity between the ‘on’ and ‘off’ states. However, the exact mechanism under-pinning these two conductivities states are not very clear. The structures used in investigation are metal-admixture-metal (MAM) and metal-insulator-semiconductor (MIS) devices. Also, glass and p-types silicon (100 orientations) with a pre-prepared Ohmic back contact were used for the MAM and MIS substrates respectively. This work will address some of the questions in regard to the electrical bistability shown by polymer memory devices.

Abstract

Phase change memories (PCM) are typically based on compounds of the Ge-Sb-Te (GST) ternary system. Nevertheless, a major drawback of PCM devices is the failure to fulfill automotive-level or military-grade requirements (125°C continuous operation), due to the low crystallization temperature of GST. To overcome this limitation, alloys belonging to the In-Sb-Te (IST) system have been proposed, which have demonstrated high crystallization temperature, and fast switching. Thermal properties of the chalcogenide alloy and of its interfaces within the PCM cell can influence the programming current, reliability and optimized scaling of PCM devices. The Modulated Photothermal Radiometry (MPTR) technique was implemented to measure the thermal conductivity of IST thin films as well as the thermal boundary resistance at the interface with other surrounding materials (a metal and a dielectric). The experiment was carried out in situ from room temperature up to 550°C in order to investigate the intrinsic thermal properties at different temperatures and the significant structural rearrangement upon the phase transition. Two different stoichiometries for the IST ternary alloy were deposited by Metal Organic Chemical Vapor Deposition (MOCVD) on a Si substrate covered with thermal SiO₂ and then capped with a Platinum layer that acts as an optical and thermal transducer. Additional data from Raman and XRD lead to complementary analysis.

Abstract

In this work we present the measurements of thermal conductivity of nanowire Sb₂Te₃ phase change. These measurements are made using a thermal scanning probe microscopy (SThM) operating in regime modulated type 3ω. The spatial resolution of the probe is of the order of 100 nm. The measurement of amplitude and phase are used to identify unknown radius of contact between the nanowire and the sensor parameters, the contact resistance at the interface probe and nanowire and the thermal conductivity of the nanowire. An identification method is used which minimizes the difference between the measured values and those from a simulated model of heat transfer in the materials. This model uses a matched model heat transfer in the probe.

Abstract

This work reports on new MRAM concepts aiming at sub-nanosecond switching and for sub-20nm technology nodes. Ultrafast precessional spin-transfer switching in nanopillars is possible to obtain in samples integrating a perpendicular polarizer and a tunnel junction with in-plane magnetized electrodes. We show that spin transfer torque (STT) switching in less than 500ps can be achieved in these structures with corresponding write energy less than 100fJ. For high density integration and possibly sub-20nm diameter cells the use of a thermally assisted concept for perpendicular anisotropy cells, where the intrinsic heating is used to simultaneously achieve high thermal stability and low current switching.

Abstract

Ferroelectrics are very interesting materials for nonvolatile data storage due to the fact that they deliver very low power programming operation combined with nonvolatile retention. For 60 years researchers have been inspired by these fascinating possibilities and have tried to build ferroelectric memory devices that can compete with mainstream technologies in their respective time. The progress of the current concepts is limited by the low compatibility of ferroelectrics like PZT with CMOS processing. Therefore, PZT or SBT based 1T1C ferroelectric memories are not scaling below 130 nm and 1T ferroelectric FETs based on the same materials are still struggling with low retention and very thick memory stacks. Hafnium oxide, a standard material in sub 45 nm CMOS, can show ferroelectric hysteresis with promising characteristics. By adding a few percent of silicon and annealing the films in a mechanically confined manner. Boescke et al. demonstrated ferroelectric hysteresis in hafnium oxide for the first time. Recently, a large number of dopants including Y, Al, Gd and Sr have been used to induce ferroelectricity in HfO₂. This paper reviews the current status of hafnium oxide based ferroelectrics, its application to field effect transistors and puts this approach into a wider context of earlier developments in the field.

Abstract

We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration with the back-end-of-line (BEOL) process to replace conventional embedded SRAM cache memories. Our MRAM technology features a top-pinned, perpendicular magnetic tunnel junction (MTJ) and a highly reliable MTJ for a cache memory. We could obtain a higher density cache memory than that with conventional SRAMs with our STT-MRAMs, and leakage free characteristics, as well as unlimited write and read cycling times and 10-year time-dependent dielectric breakdown (TDDB) characteristics. They were integrated into Cu interconnects with 300 mm facilities. We also discuss variations in MTJ pattern sizes that are very important for memory applications from the viewpoint of high density embedded cache memories.